Abstract
Timing elements, latches and flip-flops, are critical to performance of digital systems, due to tighter timing constraints and low power requirements. Short setup and hold times are essential, but often overlooked. Recently reported flip-flop structures achieved small delay between the latest point of data arrival and output transition. Typical representatives of these structures are sense amplifier-based flip-flop (SAFF), hybrid latch-flip-flop (HLFF) and semi-dynamic flipflop (SDFF). Hybrid flip-flops outperform reported sense amplifier-based designs, because the latter are limited by the output latch implementation. SAFF consists ofthe sense amplifier in the first stage and the RS latch in the second stage.
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