Semi-deterministic fault-independent test generation and its impact on ATPG performance

Abstract

A new semi-deterministic fault-independent test generation (SDTG) method suitable for phase I of automatic test pattern generation (ATPG) systems is introduced. The new method combines the advantages of random test generation (RTG), parallel pattern, single fault propagation, and maximizes the number of detected faults in phase 1 by deriving test vectors from those already simulated. The new method has been implemented in an ATPG system to assess its performance. Experimental results obtained from the 1SCAS85 benchmark circuits show that the fault coverage achieved in phase I by the proposed SDTG method is higher than that obtained by using RTG. The total test generation time for several of the benchmark circuits improved by up to 17% while achieving the same overall fault coverage. The extra time spent in phase 1 by the new SDTG method is more than repaid by the reduction in time needed in phase II, and therefore reduces the total test generation time for most circuits.