Self-Terminated Write-Assist Technique for STT-RAM

Abstract

The main challenge in the programming of spin transfer torque (STT)-RAM is to reduce the associated power consumption without the increase in area. This paper proposes a novel self-terminated write-assist technique to cutoff the unnecessary writing power consumption and then compares its delay and writing power consumption with the previously reported technique along with the area required. Programming of magnetic random access memory array is done by bi-directional current flow (i.e., STT) that enables high density along with write monitoring system for determining the write termination. A Verilog-A compact model of the magnetic tunnel junction along with 45-nm CMOS technology is used for the simulation. Monte Carlo simulation is performed for proving the robustness of the proposed design. An energy and area reduction, of up to 41% and 67%, respectively, with the same delay, are obtained compared with the previously reported technique.