Abstract
In this study, a self-shut-off pulsed latch (SSPL) is proposed as sequencing elements for reducing the hold time constraint. As SSPL captures the data input after the clock edge, the large setup-time problem that exists in the master–slave flip-flop (MSFF) is eliminated. In addition, the transparency windows are closed immediately after successfully capturing the data input (self-shut-off), and the proposed SSPL is devoid of the large hold-time problem existing in conventional pulsed latches. According to the 7-nm FinFET postlayout simulation results, the sequencing timing overheads improved by 40% and 36% in SSPL, in comparison with the conventional MSFF at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {DD}} =0.4$ </tex-math></inline-formula> and 1.0 V, respectively. Furthermore, the hold time reduced by 54% and 58% in SSPL and at <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$V_{\mathrm {DD}} =0.4$ </tex-math></inline-formula> and 1.0 V, respectively, in comparison with the conventional pulsed latch.
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