Self-Organising Maps in Computer Aided Design of electronic circuits

Abstract

Computer Aided Design (CAD) of electronic circuits is very dependent on effective optimization algorithms. Several neural network paradigms have been explored in application to optimization problems in CAD and Kohonen's self-organizing maps (SOM) have proved to be one of the most successful. It focuses on mapping to SOM scheduling, and binding the processes that are crucial for optimizations in high level synthesis (HLS). Research on hardware synthesis provides methodology and optimization algorithms for automation of the design process. As the design problems span from placement of transistors to simulation or testing of a whole system, a large variety of different optimization algorithms can be found in research literature. Among those investigated lately are approaches based on neural networks and self organization maps apply to lower level hardware design problems. As the need for higher level tools increases rapidly, it is of much interest to explore the possibilities created by those new approaches in this area. The SOM based algorithms have been implemented and have formed the optimization kernel of the synthesis system SYNT that was later developed into a commercial tool.