Self-aligned (top and bottom) double-gate MOSFET with a 25 nm thick silicon channel

Abstract

In this paper, we report a fabrication method that attains the ideal double-gate MOSFET device structure. The top and bottom gates are inherently self-aligned to the source/drain. The source/drain is a fanned-out source/drain structure, which provides a low parasitic resistance. Channel silicon thickness is determined by a planar film deposition process with good uniformity control in principle. N-channel double-gate MOSFET's with a 25 nm thick silicon channel were successfully demonstrated.