Self-aligned T-gate InP HEMT realisation through double delta doping and a non-annealed ohmic process

Abstract

A self-aligned T-gate technology for lattice-matched InP HEMTs is presented which addresses the issue of the maximization of sub 100 nm gate length device performance through the reduction of source and drain parasitic resistances. The material structure used is designed to allow the use of a non-annealed ohmic contact process, resulting from the optimization of vertical conductance through the layer stack by the introduction of an additional layer of delta doping. Use of the non-annealed process in turn allows a self-aligned process flow to be adopted reducing parasitic access resistance. In addition, carrier concentration and hence horizontal conduction through the structure is increased complementing the self-aligned process in the reduction of parasitic resistances. Self-aligned devices of 70 nm gate length were fabricated and demonstrated excellent characteristics at both DC and RF including a peak transconductance of 1500 mS/mm and an f T of 270 GHz.