Self-aligned double patterning of 1× nm FinFETs; A new device integration through the challenging geometry

Abstract

FinFETs are now widely accepted transistor architecture to replace the two dimensional (2D) metal-oxide-silicon field effect transistors (MOSFETs) into a three dimensional (3D), multi-gate (MG) MOSFETs. The MG FinFETs can be fabricated either on a silicon-on-insulator (SOI) substrate or on a bulk silicon substrate. Both approaches require an advanced patterning not only to improve device performance but also to increase the packing density. Despite the simpler process and the benefit of scaling the fin dimension on an SOI substrate, the Si industry prefers the bulk FinFETS owing to their compatibility with the existing CMOS infrastructure and to the reduced wafer cost. The combination of an advanced patterning such as self-aligned-double-patterning (SADP) and a 1× nm FinFETs device fabrication on a bulk Si substrate poses very challenging geometry constraints for the process integration. In this work, the technical and geometrical challenges of a SADP bulk FinFETs process integration are outlined. Finally, an empirical model to establish robust SADP bulk FinFETs integration is presented.