Self-Controlled High-Performance Precharge-Free Content-Addressable Memory

Abstract

Content-addressable memory (CAM) is a hardware search-engine used for parallel lookup that assures high-speed match but at the cost of higher power consumption. Both low power NAND-type and high-speed NOR-type match-line (ML) schemes suffer from requirement of the precharge prior to the search. Recently, a precharge-free ML structure has been proposed but with inadequate search performance. In this brief, a self-controlled precharge-free CAM (SCPF-CAM) structure is proposed for high-speed applications. The proposed architecture is useful in applications where search time is very crucial to design larger word lengths. The proposed $128 \times 32$ -bit SCPF-CAM structure has been implemented using predictive 45-nm CMOS process and simulated in SPECTRE at the supply voltage of 1 V. The ML delay using the proposed SCPF-CAM architecture has been reduced by 88% and 73% compared to the precharge-free and traditional NAND-type ML structure.