Self-Amplified Dual Gate Charge Trap Flash Memory for Low-Voltage Operation

Abstract

We propose a self-amplified charge trap Flash memory using the dual-gate (DG) mode operation based on the capacitive coupling between the front-gate and back-gate as a promising next-generation nonvolatile memory. It is found that the coupling ratio and memory window strongly depend on the thickness of the buried oxide (BOX) layer in the silicon-on-insulator (SOI) substrate. As the BOX thickness of the SOI substrate increases, the coupling ratio and memory window of Flash memory cells increase. The DG mode can obtain a larger memory window, reduced operation voltage, and improved reliability compared with the conventional single-gate mode operation.