Abstract

In this work, the nonlinear (NL) characteristics of bi-layer high-k/low-k dielectrics structure, i.e. high-k layer with the low-k layer, are for selectorless oxide-based resistive random-access memories (RRAM) memory array application. It has been shown that such structure enhances the read currents at full read voltage (∼10-3 A) as compared to the bi-layer low-k/low-k structure (∼10-4 A), reduces low-voltage current, increases I-V nonlinearity and thereby suppresses the sneak path currents in the selectorless RRAM. Improved seasoning effect has also been demonstrated using the bilayer dielectric structure. The Fowler-Nordheim tunneling behavior has been found in the first RESET process (-0.45 to -1.25 V) as followed by the high self-rectifying characteristics that enlarge the immunity to the sneak path current and reduce the read errors in the array applications. The breakdown controllability of the forming process dominates the followed seasoning cycles which leads to two different performances in bilayer stacks i.e. efficient seasoning and inefficient seasoning, which provides an intrinsic design of selectorless RRAM devices. The device characteristics with current transport mechanisms have also been investigated. Our results provide additional insights into ways to achieve high performance and excellent reliability of built-in nonlinearity in selectorless RRAM (NL > 120, memory window > 100, sub-μs switching speed, and NL retention) for the future low-power RRAM memory array configurations.

Highlights

  • In recent years, resistive random access memory (RRAM) has drawn much interest as a promising candidate for next-generation nonvolatile emerging memory due to its potential scalability beyond 10 nm feature size (4F2 design rule), compatibility with a crossbar structure with CMOS integration, intrinsic fast switching speed (

  • It has been found that the high-k layer was utilized as the oxygen reservoir with higher oxygen concentration, which improves the nonlinearity by efficiently increasing the read current at the full-read voltage (IVread); while the identical low-k layer used for suppressing the low-voltage current i.e. HfOx/graphite and SiOx/graphite devices

  • The SET process for graphite-based resistive random-access memories (RRAM) was performed by applying to 3 V forward/reverse double sweep with 1 mA compliance current limits (CCL) to program to low resistance state (LRS)

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Summary

Introduction

Resistive random access memory (RRAM) has drawn much interest as a promising candidate for next-generation nonvolatile emerging memory due to its potential scalability beyond 10 nm feature size (4F2 design rule), compatibility with a crossbar structure with CMOS integration, intrinsic fast switching speed ( 120, memory window > 100, sub-μs switching speed, and NL retention) for the future low-power RRAM memory array configurations.

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