Selective State Retention Power Gating Based on Formal Verification

Abstract

This work is aimed to reduce the area and power consumption in low-power VLSI design. A new selective approach for State Retention Power Gating (SRPG) based on Module Checking formal verification techniques is presented, and so-called Selective SRPG (SSRPG). The proposed approach is applied in order to minimize the number of retention flip flops required for state retention during sleep mode. The proposed technique automatically selects a reduced set of retention flip flops which include only the indispensable flip flops required for a proper state recovery using some unique criteria. The criteria are represented as a set of formal properties using propositional formulas to analyze the flip-flop's input equations. Those properties are expressed in temporal logic formalism, specifically, in Computation Tree Logic (CTL). The extraction of the essential retention flip flops is carried out using common formal verification techniques. This work suggests an efficient alternative to the conventional SRPG and PG techniques. The proposed approach has been applied to a practical design with about 3000 FFs. The results demonstrate a saving factor of about 80% comparing to SRPG and thus reducing area, static power consumption and synthesis tool convergence run time. This leads to significant potential area reduction of up to 10% of the total chip area and similar energy impact. Other few published related SSRPG techniques require either exhaustive simulations or impractical design representation, and are not aimed to classify a specific flip flop in a given physical design. To the best of our knowledge this is the first time common Formal Verification Tools are used for applying a Selective SRPG approach.