Clustering based merging Flip Flop and latch technique for power optimisation

Abstract

Reducing power acting a vital role in low power VLSI design. Reducing the power consumption not only can boost battery life but also can avoid the overheating problem, which would increase the difficulty of packaging or cooling. Multi-bit flip-flop is an effective power-saving implementation method by merging single-bit flip-flops in the design. Compare the performance of both single bit flip flop and multi bit flip flop. These results in favor of Multi-Bit Flip-Flop as decrease of Clock network such as clock buffer and gate delay. In this paper, we propose agglomerative clustering algorithm to find the nearby clustering of flip flops for merging the flip flops. This algorithm finds the clusters of flip flop and finally join FFs to reduce the wire length.