Selective scan slice repetition for simultaneous reduction of test power consumption and test data volume

Abstract

In this paper, we present a selective scan slice encoding technique for power-aware test data compression. The proposed scheme dramatically reduces test data volume via scan slice repetition, and generates an adjacent-filled test pattern known as the favorable low-power pattern mapping method. Experiments were performed on the large ITC'99 benchmark circuits, and results show the effectiveness of the proposed method.