Selective epitaxial growth of silicon in pancake reactors

Abstract

Selective epitaxial growth (SEG) of silicon opens new avenues in electronic device design by allowing vertical (three dimensional) integrated circuits to be fabricated and isolation between devices to be vastly improved. In this work selective epitaxial silicon deposition is performed in an RF-heated pancake reactor onto three inch SiO 2 masked (100) silicon wafers. Dichlorosilane (SiH 2Cl 2) is used as the silicon source and HCl is continuously fed into the reactor so that nucleation of silicon on SiO 2 is prevented. Growth rates are found to be on the order of 0.1 μm/min at a total reactor pressure of 150 torr and a substrate temperature greater than 900 ° C. A new detailed mathematical model of SEG in a pancake reactor is presented. It includes all mass, energy and momentum equations coupled with the special geometry, inlet and exhaust configuration typically used in pancake reactors. Predictions from our mathematical model are seen to be in satisfactory agreement with data obtained in the RF-heated Purdue pancake reactor. Some recommendations with respect to the optimization of such systems are also discussed.