Selection of PWM Methods for Common-Mode Voltage and DC-Link Capacitor Current Reduction of Three-Phase VSI

Abstract

This paper evaluates several important pulse-width modulation (PWM) methods developed to reduce the common-mode voltage (CMV) or DC-link capacitor current (DCC) of two-level three-phase voltage source inverter (VSI) in motor drive applications. In addition, a PWM selection criterion is introduced to properly utilize these advanced PWM methods in the VSI system. In the motor drive systems, the high CMV generates the large common-mode current, which may cause electromagnetic emissions and motor damages. Also, the large DCC may have an adverse effect on the life expectancy and increase the volume of DC-link capacitor. Therefore, reducing the CMV and DCC is required in modern VSI systems. So far, various PWM methods have been studied to reduce these CMV and DCC. However, they need to be fairly compared and evaluated together under the same condition to provide information so that power electronics engineers can select the appropriate PWM method when designing their motor drive systems. In this paper, the principle of these PWM methods is reviewed and their performance is analytically evaluated. Then, the PWM selection criterion is described based on the comprehensive evaluation studies. Lastly, the simulation and experimental results with an interior permanent magnet synchronous motor (IPMSM) drive system are presented to validate the presented PWM selection criterion.