Selection of Crosstalk-Induced Faults in Enhanced Delay Test

Abstract

Current design trends have shown that crosstalk issues in deep sub-micron can cause severe design validation and test problems. In this paper, we address the problem of enhanced delay test considering crosstalk-induced effects. Two types of crosstalk-induced delay fault model in related works are analyzed according to their relationship to common delay fault models. The difficulties in test generation using these fault models are shown. Based on the discussion, a single precise crosstalk-induced path delay fault model, S-PCPDF model, is proposed for circuits given delay assignment. A target S-PCPDF fault gives information on a sub-path to be sensitized to generate necessary transitions coupled to a critical path. It is then convenient to enhance conventional path delay fault ATPG algorithms to implement ATPG systems for crosstalk-induced path delay faults by adding the constraints on the sub-path. We then propose two approaches to reducing the number of target S-PCPDF faults. One is based on constraints for side-inputs of paths under test. The other is based on pre-specified states during test generation for the critical path. Experimental results on ISCAS'89 benchmark circuits showed that the proposed approaches can reduce the number of target faults significantly and efficiently. The CPU time for fault list reduction and test pattern generation is acceptable for circuits of reasonable sizes.