Abstract
An increase in vulnerability to soft errors has affected the reliability of both synchronous and asynchronous nanometer scale integrated circuits. Hence in such circuits there is a growing need to identify the soft error glitch propagation possibility before their physical design implementation. This paper proposes a new tool, the Soft Error Glitch-Propagating path Finder (SEGP-Finder), able to analyze the propagation of soft errors at gate level. In SEGP-Finder, soft error modeling is accomplished via Multiway Decision Graphs (MDGs) and Glitch Propagation sets (GP sets). To demonstrate the effectiveness of our tool, several ISCAS89 sequential benchmark circuits, 4-bit and 8-bit adders, 4-bit multiplier, and the Self-timed multiple-group pipeline asynchronous handshake circuit have been analyzed. Results indicate that SEGP-Finder is on average more than 5 times faster, without compromising on the accuracy, in comparison with simulation-based and SAT (satisfiability analysis) based techniques.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
