Abstract
The authors report the results of a study on the impact of resistive bridging faults on triple modular redundancy (TMR)-based quasi-delay-insensitive (QDI) asynchronous countermeasures, which is used to provide a secure circuit against power analyses. They have carried out the present study on CADENCE using a resistive bridges fault model. They show that the resistive bridge faults can have serious impacts on the security of integrated circuits and it is possible to discover the secret data. Based on the bridges resistance value, there are three operating intervals of secure circuits, in which TMR-based QDI may or may not function correctly in the presence of two resistive bridge faults depending on the interval of the resistance value.
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