Secure Information Processing during System-Level: Exploration of an Optimized Trojan Secured Datapath for CDFGs during HLS Based on User Constraints

Abstract

Globalization of the System-on-Chip (SoC) design process poses a serious security alarm for SoC integrators, due to involvement of untrustworthy third party (3P) vendors supplying intellectual property (IP) cores. In this paper, a novel methodology for design space exploration in high level synthesis (HLS) is presented for loop based control data flow graphs (CDFG), which provides secure information processing against hardware Trojan in 3PIPs. The proposed approach performs this system level protection by exploration of an optimized combination of Trojan secured dual modular redundant (DMR) data path and loop unrolling factor (U) by employing a novel particle swarm encoding scheme. Further, the approach also presents a novel technique for efficient exploration of vendor allocation procedure for hardware capable of Trojan detection. Finally, the approach presents a novel area-delay tradeoff during exploration of Trojan secured data path and unrolling factor. Results indicated an average improvement in Quality of Results (QoR) of ~12% compared to a similar prior research.