Abstract
Bulk Schottky silicide source/drain n- and p-MOS transistors (SSDTs) with EOT=2.0 /spl sim/ 2.5nm HfO/sub 2/ gate dielectric and HfN/TaN metal gate have been successfully demonstrated using a low temperature process. P-SSDTs with PtSi silicide show excellent electrical performance of I/sub on//I/sub off//spl sim/ 10/sup 7/ - 10/sup 8/ and subthreshold slop of 66 mV/dec. N-SSDTs with YbSi/sub 2-x/ silicide have also demonstrated a very promising characteristic with a recorded high I/sub on//I/sub off/ radio of /spl sim/ 10/sup 7/ and subthreshold slope of 75mV/dec. To the best of our knowledge, these are the best SSDTs data reported so far. The implant free low temperature process relaxes the thermal budget of high-K dielectric and metal gate materials. Our results are expected to be further improved when using ultra-thin-body (UTB) SOI structures, showing great potential of this low temperature process SSDTs for future sub-tenth micron CMOS technology.
Published Version
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