Abstract
3D Finite Element (FE) Monte Carlo (MC) simulation toolbox incorporating 2D Schrödinger equation quantum corrections is employed to simulate ID-VG characteristics of a 22nm gate length gate-all-around (GAA) Si nanowire (NW) FET demonstrating an excellent agreement against experimental data at both low and high drain biases. We then scale the Si GAA NW according to the ITRS specifications to a gate length of 10nm predicting that the NW FET will deliver the required on-current of above 1mA/μm and a superior electrostatic integrity with a nearly ideal sub-threshold slope of 68mV/dec and a DIBL of 39mV/V. In addition, we use a calibrated 3D FE quantum corrected drift-diffusion (DD) toolbox to investigate the effects of NW line-edge roughness (LER) induced variability on the sub-threshold characteristics (threshold voltage (VT), OFF-current (IOFF), sub-threshold slope (SS) and drain-induced-barrier-lowering (DIBL)) for the 22nm and 10nm gate length GAA NW FETs at low and high drain biases. We simulate variability with two LER correlation lengths (CL=20nm and 10nm) and three root mean square values (RMS=0.6,0.7 and 0.85nm).
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