Scalable techniques and tools for reliability analysis of large circuits

Abstract

With the rapid advancement of CMOS and non-CMOS nanotechnologies, circuit reliability is becoming an important design parameter. In recent years, a number of reliability evaluation methodologies based on probabilistic model checking, probabilistic transition matrices, etc., have been proposed. Scalability has been a concern in the wide applicability of these methodologies to the reliability analysis of large circuits. In this paper, the similarities between these reliability evaluation methodologies were discussed and focus mainly on the scalability issue. In particular, a scalable technique for the model checking-based methodology was developed, and how this technique can be applied to the other methodologies was shown. A tool called SETRA was also developed that can be used to integrate the scalable forms of these methodologies in the conventional circuit design flow