Scalable Modeling of MOSFET Source and Drain Resistances for MS/RF Circuit Simulation

Abstract

Large-width and short-length MOS transistors with multi-finger layouts are necessary for the mixed-signal and RF IC designs to achieve optimum gain and noise performances. As the total width (i.e., the product of the finger width and the number of fingers Nfg) increases, the parasitic source and drain resistances due to the contact and diffusion regions becomes comparable in magnitude to the MOSFET intrinsic channel resistances under many (bias and layout) scenarios and, hence, require accurate and scalable SPICE modeling. This paper presents a model for multi-finger MOSFET source /drain contacts and diffusion parasitic resistances, and a simple parameter extraction methodology to take into account the unwanted parasitic impacts from the wiring and measurement equipment; both can be readily applied to BSIM3v3 and BSIM4. Excellent accuracy and scalability have been achieved in comparison with measurement