Scalable counter architecture for a pre-loadable 1 GHz@0.6 μm/5V pre-scaler in TSPC

Abstract

In this paper we describe an approach for using the true single phase clock (TSPC) circuit style for the implementation of a scalable, pre-loadable pre-scaler. By utilization of a signed digit (SD) based redundant adder cell the execution of the necessary addition operation can be performed in only one clock cycle, independent of the length of the applied operators. The development process for this SD-adder cell by reorganization and partitioning of the necessary logic in connection with an enhancement of the TSPC circuit style will be discussed. The determination of the zero-crossing is also as far as possible independent from the word length by deployment of a TSPC OR-cell. Furthermore, a reference implementation of a 8-digit pre-scaler circuit operating at 1 GHz with a 5 V power supply in a 0.6 /spl mu/m AMS CMOS process will be presented. The goal of this paper is to develop a strategy for the implementation of pre-scaler circuits based on redundant arithmetic, which can operate at high frequencies. The comparison with the results of other implementations illustrate the advantages of our approach.