Abstract
Floating Gate (FG) NAND scaling has been severely challenged by the reduction of gate coupling ratio (CR) and increase in FG interference (FGI) below 30nm node. Firstly, scalability of inverted "T" shaped FG is evaluated by 3D electrostatics simulation. It is shown that coupling ratio (CR) and Floating Gate Interference (FGI) performance can be maintained at the level of 34nm technology down to 13nm node by engineering key aspects of the FG shape namely FG top width (FGW) and effective field height (EFH) in addition to conventional scaling approaches of IPD thinning and spacer k reduction. Secondly, FG shaping is demonstrated down to FGW of 3nm and EFH of 5nm using a sacrificial oxidation technology with no bird's beak to demonstrate fabrication feasibility.
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