(Invited) Influence of Post Deposition Annealing on the Electrical Properties of Pt-Ti/HfO2/TiN/Sion/n-Si Capacitor for Flash Memory Applications

Abstract

To address the cell-to-cell interference in conventional floating gate (FG) flash memory, a fully planar structure demands continuous scaling of poly silicon floating gate thickness. But the reduced FG thickness causes reliability issues due to ballistic current through inter-poly dielectric (IPD) and also decreases the gate coupling ratio (GCR). The introduction of metal FG in flash memory eliminates the problem of poly depletion and ballistic transport even with ultrathin floating gate (<10 nm) and excellent memory performance with 16 V P/E window for 1 nm metal floating gate. Numerous studies on flash memory devices reported that a hybrid FG, transition metal dichalcogenides and multilayer graphene as FG results in improved memory performance such as fast program speed, excellent data retention and endurance characteristics. According to ITRS scaling projections for FG NAND flash, GCR of 0.6-0.7 would be desirable for satisfactory operation. However, in order to obtain adequate GCR, high-k based IPD and/or tunnel barrier has been proposed as mandatory alternatives. The improvement in GCR owed to greater coupling between the control and floating gates as a result of increased dielectric constant. The incorporation of nitrogen into tunnel oxide of NVM through nitridation can enhance the reliability performance of tunnel oxide of charge storage NVM. In this paper, we report the fabrication of Pt-Ti/HfO2/TiN/SiON/n-Si capacitor for flash memory applications with gate coupling ratio (GCR) of 0.68 and 0.71 for as-deposited and annealed SiON respectively. The XRD, AFM, FTIR, FESEM and XPS characterizations have been performed for structural and morphological studies. Program/erase and retention characteristics reveal the largest memory window of approx. 11.2 V after post deposition annealing and excellent data retention at room temperature under ±10 V. The enhanced program/erase speed was due to the fact that annealed SiON tunnelling oxide provides stronger interface against Si dangling bond generation and the decrease in barrier height of both electrons and holes. These results indicate that the SiON tunnelling oxide can be engineered by post deposition annealing for the improvement of metal floating gate memory performance.