Scalability and Reliability Characteristics of CVD HfO2 Gate Dielectrics with HfN Electrodes for Advanced CMOS Applications

Abstract

Metal-oxide-semiconductor (MOS) devices using a thermally robust gate stack were fabricated. The equivalent oxide thickness of gate stack has been aggressively scaled down to 0.75 and for MOS capacitors and metal-oxide-semiconductor field effect transistors, respectively, after a thermal budget required by the conventional complementary metal-oxide-semiconductor gate-first process. The reliability issues such as time-dependent dielectric breakdown (TDDB) and bias temperature instability (BTI) of the devices are studied. The stress electric-field-dependent TDDB characteristics are demonstrated and explained by a model taking into account the high energetic carrier trapping in the and at the interfacial layer. The polarity dependent BTI characteristics are observed which can be explained by a generalized reaction-diffusion model. These intrinsic reliability characteristics are correlated with the low pre-existing charge traps in gate stack resulting from a high temperature postdeposition annealing of the gate stack.