Saturation mechanism in 1-µm gate GaAs FET with channel—Substrate interfacial barrier

Abstract

The evolution of the drain saturation current of the carrier concentration and of the equipotential lines in a GaAs MESFET, were studied taking into account the existence of an interfacial barrier between the active layer and the SI substrate. A bidimensional numerical simulation was used either in a classical finite-difference model with quasi-static velocity versus field characteristic, or as a particle-diffusive model using an energy-dependent mobility and nonstationary electron dynamics were taken into account. The authors show that the difference between the experimentally observed continuous increase in drain current and the decrease predicted by models using the symmetrical FET approximation can be understood by a channel widening under the influence of the trapped dipole domain. A subsequent analytical model, giving quantitative prediction for g <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</inf> and g <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</inf> is then proposed.