Salient Features in the Capacitance Characteristics of Ultrathin High-K Devices

Abstract

Salient features of MOS (Metal Oxide Silicon) devices with ultra-thin high-Κ gate dielectrics are outlined here, which include the following. In the case of the ultra-thin (EOT < 2 nm) gate dielectrics, the capacitance-voltage (C-V) and the surface potential versus bias characteristics are dominated by the accumulation and the strong inversion regimes, in contrast to the case of the thicker gate dielectrics, where these characteristics are dominated by depletion and weak inversion regimes. In the strong accumulation regime, the experimental lnCp versus the surface potential plot (Cp is the sum of the space charge capacitance Csc and the interface trap capacitance Cit) was found to be a straight line, and its slope varied strongly with the gate dielectric material and was found to be inversely proportional to [square root(Pbm*/m)]K/Cdi, where Pb is the conduction/valence band offset, m* is the effective electron/hole tunneling mass, K is the dielectric constant, and Cdi is the gate dielectric capacitance.