Run-Time Thermal Management for Lifetime Optimization in Low-Power Designs

Abstract

In this paper, the magnitude of the temperature and stress variability of dynamic voltage and frequency scaling (DVFS) designs is analyzed, and their impact on the bias temperature instability (BTI) degradation and lifetime of DVFS designs is assessed. For this purpose, a design-time evaluation framework for BTI degradation was developed, which considered the statistical workload and die temperature profiles of DVFS operating modes. The performed analysis showed that, together with high stress variability, DVFS designs exhibited even higher temperature variability, depending on the workload and utilized operating modes, and the impact of temperature variability on lifetime could be up to 2× higher than that due to stress. In order to account for temperature variability on aging detrimental effects, a thermal management run-time system is proposed that honors the desired lifetime constraints by properly selecting temperature constraints that govern the utilized operating modes. The proposed run-time system was applied on the largest benchmark circuit from the IWLS 2005 suite, Ethernet circuit, synthesized with the 32 nm CMOS technology. The proposed system was verified to obtain lifetime and performance estimation and the trade-off with up to 35.8% and 26.3% higher accuracy, respectively, when compared to a system that ignores temperature variability and accounts for average temperature only. The proposed framework can be suitably utilized for tuning run-time throttling policies of low-power designs, thus allowing designers to optimize lifetime–performance trade-offs, depending on the requirements mandated by specific applications and operating environments.