Run-Time Reconfigurable Instruction Set Processor design: RT-RISP

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Reconfigurable Instruction Set Processors are the next generation processors, which can optimize their instruction sets according to the applications being under execution on them. This optimization is achieved through reconfiguration in their hardware on fly. In this way the reconfigurable processors adapt their hardware, which is most suitable one for the running application and consequently they enhance the performance. Reconfigurable instructions set processors are the programmable processors that contain the reconfigurable logic in one or more of their functional units. The hardware design of such type of processors can be categorized into two main tasks: The design of reconfigurable logic itself and the design of the communication interface of reconfigurable logic with the remaining modules of the processor. Among the most important parameters of the design are, the granularity of the reconfigurable logic, the structure of configuration memory, the instructions encoding formats and the type of the instructions supported. In this research paper a Run-Time Reconfigurable Instruction Set Processor design has been presented with the property of partially, run-time reconfigurable. The proposed processor supports the demand driven modification of its instruction set. It treats the instructions as removable modules that can be paged in and paged out through partial reconfigurations as demanded by the running applications.