RTOS-supported low power scheduling of periodic hardware tasks in flash-based FPGAs

Abstract

As flash-based technology features inherently a lower power consumption than SRAM-based technology, flash-based FPGAs are well suited for energy-aware applications that are often found, e.g., in battery-powered embedded systems. Additionally, power gating allows to shut down large parts of an FPGA during idle times, reducing the energy consumption even further. When power gating SRAM-based FPGAs, the configuration memory is erased. The current state has to be stored and reconfigured in a time intense process before hardware accelerators can be used again. By contrast, in flash-based FPGAs the configuration memory and register contents are retained. In Microsemi / Microchip devices, the power gating mode is called Flash*Freeze. As only the complete FPGA can be put into Flash*Freeze mode, its applicability is reduced when many hardware tasks with different execution times share the same FPGA. This problem is tackled by the cluster scheduling algorithm presented in this paper. It modifies the schedule of hardware tasks under consideration of their real-time constraints in order to prolong Flash*Freeze phases. We describe its integration into the real-time operating system FreeRTOS, which allows to hide technical details from the applications and provides an easy-to-use interface. For a task set with sufficient overlapping task instances, the cluster scheduling algorithm reduces energy consumption on average by 33.5% in comparison to applications that do not employ the Flash*Freeze mode and by 22.5% in comparison to applications that use the Flash*Freeze mode with an unchanged schedule. In the best case, a prolongation of the Flash*Freeze mode in the order of n can be reached with n given hardware tasks.