Abstract
In many cities, traffic regulation is a difficult challenge to solve. This is due to the large number of cars and the traffic system’s high dynamics. Poor traffic network are a major cause of accidents and lost time. Vehicles will spend a minimum waiting period at traffic lights if this methodology is used. Verilog Hardware Description Language (HDL) programming is used to create the hardware design. Verilog is a hardware description language that deals with hardware design and simulation, as the name indicates. Mounting the numerous electronic components on a breadboard or PCB circuit becomes quite complex. It also takes an excessive amount of time to simulate, and various faults might arise due to poor component connections on the circuit. As a result, hardware descriptive language concludes to overcome this obstacle. The fundamental design of a T-shaped road for traffic light regulation is the subject of this project. Mentor Graphics, Questasim and Oasys has been used to test the system’s output.
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