Abstract
Subthreshold circuit designs are very much popular for some of the ultra-low power applications, where the minimum energy consumption is the primary concern. But, due to the weak driving current, these circuits generally suffer from huge performance degradation. Therefore, in this paper, we primarily targeted analyzing the performance of a near-threshold circuit (NTC), which retains the excellent energy efficiency of the subthreshold design, while improving the performance to a certain extent. A modified row-based dual Vdd 4-operand carry save adder (CSA) design has been reported in the present work using 45 nm technology. Moreover, to find out the effectiveness of the near-threshold operation of the 4-operand CSA design, it has been compared with the other design styles. From the simulation results, obtained for the frequency of 20 MHz, we found that the proposed scheme of CSA design consumes 3.009 ×10-7 Watt of average power (Pavg), which is almost 90.9% lesser than that of the conventional CSA design, whereas, looking at the perspective of maximum delay at output, the proposed scheme of CSA design provides a fair 44.37% improvement, compared to that of the subthreshold CSA design.
Highlights
Subthreshold digital circuit design is a well-practiced technique, for implementing the highly energy-constrained, ultra-low power applications such as implanted sensors, pacemakers, and mobile peripheral processors [1, 2]
In the first case, where Vdd is set to 0.4 Volt and frequency is 200 MHz, we considered the different width of the PMOS (Wp)/width of the NMOS (Wn) values for the transistors used in the buffer circuit
When the gate length (L) = 45 nm, Wp/Wn = 800 nm/200 nm, we found that the Pavg of the circuit is 3.528 × 10−8 Watt and the td max is 1.378 × 10−10 Second
Summary
Subthreshold digital circuit design is a well-practiced technique, for implementing the highly energy-constrained, ultra-low power applications such as implanted sensors, pacemakers, and mobile peripheral processors [1, 2]. On the other hand, assigning the dual Vdd scheme to a CMOS circuit can be very effective in reducing both the dynamic and the leakage power [5, 6] It provides the higher supply voltage (VddH) to timing critical logic gates, whereas the other noncritical logic gates of the circuit are driven by a lower supply voltage (VddL). With this dual Vdd technique, it is possible to reduce the overall power consumption, without degrading the performance of the circuit too much [2, 4].
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