Routing Strategy: Network-on-Chip Architectures

Abstract

Network-on-chip (NoC) is a special and unique case of parallel computing systems defined by tight constraints such as availability of resources, area, cost of the NoC architecture and power consumption. A NoC is designed of three main components: switches, network interfaces (NIs), and links. It is a technology that is proposed to solve the shortcoming of buses. This technique is to design communication subsystem among IP cores (intellectual property core) in a SoC design. The strategy by which bundles are guided from source to destination can be deterministic, unaware, or versatile. Systems with no way differences are compelled to utilize deterministic directing techniques; different topologies may utilize unaware or versatile calculations. The three important things to design NoC is topology, routing mechanism and switching algorithm. The topology defines how to interconnect the nodes in the network and switch is enabled after receiving the header of the packet that contains the information about the destination address. The switch input channel is connected to the output channel. There are many switching 168techniques used: store- and forward switching, cut-through switching, and wormhole switching. The routing algorithm and network topology are the two important aspects for on-chip communication in NoC. The router makes the path for the received packet to the destination. The main property of route in NoC should make the path to error-free, deadlock-free, and highest performance. The route in the NoC is divided into two parts, one is the source node which makes the path before packet leave from the source, and another one is the destination route which make the path based on the information given in the header of the packet.