Room-temperature demonstration of low-voltage and tunable static memory based on negative differential conductance in silicon single-electron transistors

Abstract

A static memory based on negative differential conductance (NDC) in silicon single-electron transistors is proposed. We fabricate a room-temperature (RT) operating single-hole transistor (SHT) in the form of an ultranarrow wire channel metal-oxide-semiconductor field-effect transistor (MOSFET), and observe clear NDC due to large quantum level spacing of an ultrasmall dot at RT. By serially connecting an SHT showing NDC and a p-type MOSFET acting as a load on a single chip, gate-controllable memory operation is demonstrated at the supply voltage of 0.2V at RT. The proposed memory features high compatibility with the existing very-large-scale integrated circuits, compact size, low-voltage, and tunable operation.