Room temperature ALD oxide liner for TSV applications

Abstract

To date, Plasma Enhanced Chemical Vapor Deposition (PECVD) O3/TEOS has been the prevalent dielectric liner for TSV applications. This process typically results in poor step coverage for high aspect ratio (HAR) TSV scenarios, and also requires a capping layer to provide acceptable reliability performance due to the high moisture content of the O3/TEOS material. This study reports on a high throughput room temperature Atomic Layer Deposition (ALD) batch process for use as a dielectric liner in TSV applications, which provides several advantages over existing processes. Process characterization was completed to achieve a 100nm thickness SiO2 liner for a 6×55µm TSV size with nearly 100% conformal sidewall coverage, demonstrating the usefulness of this process for scaling to 3×50µm TSV size and beyond. Characterization of the ALD SiO2 dielectric liner showed breakdown voltage, leakage, and parasitic capacitance values as good as, or better than, the PECVD O3/TEOS dielectric process of record. In addition, the batch ALD process allows for a significant cost reduction of the overall TSV module. The new ALD SiO2 dielectric liner material was also validated through the downstream TSV fabrication process with no adverse effects.