Role of source/drain junction on plasma induced gate charging damage in N MOSFET

Abstract

The effect of source and drain junctions on plasma induced gate charging damage in NMOSFETs is explored. NMOSFETs with a grounded source, a common configuration in CMOS circuits, can experience significant gate oxide damage during a plasma event. Increasing source and drain diffusion size can enhance charging damage in the gate oxide. This damage can be eliminated or minimized by attaching an efficient protecting device such as a gated diode at the transistor gate. This protection device occurs quite naturally in CMOS circuits such as inverters. All the charging effects described can be explained by a model taking into account the reverse-biased source- and drain-to-substrate junction under plasma illumination, and the silicon potential near the source and along the gate channel. Simulation based on this model suggests that plasma illumination, in addition to thermal carrier generation, plays a significant role in damage formation in gate oxide during the plasma process event.