Role of process gases in making tapered through-silicon vias for 3D MEMS packaging

Abstract

This article report a continuous plasma etching process using SF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sub> /O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Ar gases for fabricating 100 μm deep tapered through-silicon vias (TSV). The flow rates of the process gases were changed to study their individual effect on the profile angle, via depth, sidewall roughness, and sideways undercut of the tapered vias. Tapered vias having profile angles varying from 70° to 85° and smooth sidewalls were etched by balancing the chemically-assisted isotropic etching of F* radicals, passivation film by O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> , and ion-assisted passivation etching. The flow rates of SF <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sub> and O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> were found to be the important factors which determine the profile angle and via surface roughness. After considering the individual effects of each gas, an optimized etching recipe was fixed, which was used to etch 100 μm deep vias having a profile angle of 83°. Insulation and seed layers were deposited by conventional low-temperature processes. The tapered vias were then partially filled by copper electrodeposition and redistribution lines were formed. The electrical resistance of tapered TSVs was measured to be between 3-8 mΩ for the majority of the TSVs.