Role of Interfacial Layer on Breakdown of TiN /High- κ Gate Stacks

Abstract

This work examines the inherent asymmetry on breakdown characteristics of the interfacial layer (IL) and high-κ layer in the overall gate-stack breakdown. Ramped and constant voltage stresses were applied on atomic-layer-deposited gate stacks. Under ramped stress when a thin high-κ layer is used, IL is responsible for the overall gate-stack breakdown; otherwise, the breakdown is initiated by the high-κ layer. Under constant voltage stress the gate stack went through many degradation mechanisms, such as charge trapping and defect generation, soft breakdown, progressive breakdown, and finally hard breakdown. In addition, when the breakdown field of ILs grown under various process conditions was compared, it was observed that for a fixed IL thickness, breakdown field does not depend on predeposition surface treatment; rather, it is a function of the quality of IL. Stress-induced leakage current was also studied to correlate with the breakdown behavior.