Breakdown Characteristics of High-k Gate Dielectrics with Metal Gates

Abstract

This work examines the inherent asymmetry on breakdown characteristics of interfacial layer (IL) and high-k layer in the overall gate stacks breakdown. Ramped and constant voltage stresses were applied on atomic layer deposited TiN/HfO2/SiO2 gate stacks. Under ramped stress when a thin high-k layer ({less than or equal to} 3.3 nm) is used, IL is responsible for the overall gate stack breakdown otherwise the breakdown is initiated by the high-k layer. Under constant voltage stress the gate stack went through many degradation mechanisms such as charge trapping and defect generation, soft breakdown, progressive breakdown and finally hard breakdown. When the breakdown field of ILs, grown on various process conditions is compared, it was observed that for a fixed IL thickness, breakdown field does not depend on pre-deposition surface treatment rather as a function of the quality of IL. Stress-induced leakage current was also studied to correlate with that of the breakdown behavior.