Abstract
With technology scaling, achieving a target read yield of resistive nonvolatile memories becomes more difficult due to increased process variation and decreased supply voltage. Recently, an offset-canceling dual-stage sensing circuit (OCDS-SC) has been proposed to improve the read yield by canceling the offset voltage and utilizing a double-sensing-margin structure. In this paper, an offset-canceling zero-sensing-dead-zone sense amplifier (OCZS-SA) combined with the OCDS-SC is proposed to significantly improve the read yield. The OCZS-SA has two major advantages, namely, offset voltage cancellation and a zero sensing dead zone. The Monte Carlo HSPICE simulation results using a 65-nm predictive technology model show that the OCZS-SA achieves 2.1 times smaller offset voltage with a zero sensing dead zone than the conventional latch-type SAs at the cost of an increased area overhead of 1.0% for a subarray size of 128 × 16.
Highlights
Resistive nonvolatile memories (NVMs) such as spin-transfer-torque random access memory (RAM) and resistive RAM promise higher density and lower power than conventional memories such as static RAM, dynamic RAM, and Flash memory [1,2,3], they suffer from degraded read yield following technology scaling due to the increased process variation, reduced supply voltage, and decreased read cell current (Iread ) [4,5,6].In general, two output voltages of a sensing circuit (SC), namely, V SA_data and V SA_ref, are introduced into a sense amplifier (SA) to generate a digital signal [7]
If RAPYCELL, which is improved by employing the offset-canceling zero-sensing-dead-zone sense amplifier (OCZS-SA), is greater than a target RAPYCELL, the total read energy in the SC and SA can be saved by reducing the SC operation time (TSC ) and/or Iread
The conventional latch-type SAs cannot be applied to the offset-canceling dual-stage SC (OCDS-SC) due to the capacitive-coupling and sensing-dead-zone problems
Summary
Resistive nonvolatile memories (NVMs) such as spin-transfer-torque random access memory (RAM) and resistive RAM promise higher density and lower power than conventional memories such as static RAM, dynamic RAM, and Flash memory [1,2,3], they suffer from degraded read yield following technology scaling due to the increased process variation, reduced supply voltage, and decreased read cell current (Iread ) [4,5,6]. The recently proposed offset-canceling dual-stage SC (OCDS-SC) has improved RAPYCELL by reducing σ∆V due to the offset voltage cancellation in the SC and by increasing μ∆V due to the double-sensing-margin structure [6]. ∆V distribution of of the the offset-canceling offset-canceling dual-stage dual-stage sensing sensing circuit circuit (OCDS-SC). In this this paper, paper, we we propose propose an an offset-canceling offset-canceling zero-sensing-dead-zone zero-sensing-dead-zone SA. SA_OS by offset-voltage cancellation zero-sensing-dead-zone capable of significantly reducing σSA_OS by offset-voltage cancellation with a zero-sensing-dead-zone characteristic. The remainder of this paper is organized as follows: Section describes the problems in conventional. The remainder of this paper is organized as follows: Section 2 describes the problems in conventional latch-type introduces proposed presents simulation results latch-typeSAs; SAs; Section. Comparison; and comparison; and Section 5 presents the conclusions drawn from our study
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