Robust High Speed Ternary Magnetic Content Addressable Memory

Abstract

Designing robust, low power, and delay ternary magnetic content addressable memory (TMCAM) using spintronic-based devices like magnetic tunnel junction (MTJ) is a challenge. Process variations in MTJ and transistor degrade the performance of ternary content-addressable memory (TCAM) as the number of bits increases. To bring TCAM using MTJ (TMCAM) to practical use for wide arrays (>2048 bits), its cell has to be designed with large tolerance to all types of variations. Reducing the power consumption associated with searching without the increase in delay is also essential for the designing of TMCAMs. The proposed TMCAM cell has guaranteed read-disturbance immunity, low delay, and comparable power as compared with the reported MTJ-based magnetic-content-addressable memory (MCAM). Monte Carlo simulation was performed for proving the robustness of the proposed TMCAM by considering both variations in MTJ and transistor parameters. A Verilog-A model of the MTJ along with 45-nm CMOS technology is used for the simulation. A delay reduction of 1.23 times with power decrement of 1.23 times is obtained compared with previously reported MCAM for TMR = 3. This leads to a power-delay product improvement of 1.5 times for 2048-bit TMCAM.