Robust and area-efficient nLDMOS-SCR with waffle layout structure for high-voltage ESD protection

Abstract

A novel waffle-type nLDMOS-SCR ESD clamp with compact source and drain for high-voltage ESD protection is proposed and realised using the 0.35 µm, 30/5 V bipolar-CMOS-DMOS (BCD) process. With this new structure, a high ESD failure current of 4.4 A was achieved with a total channel width of only 60 µm. Considering the area efficiency, the waffle-type structure provides more than 30% higher current handling capability than the conventional ones. Because of its better robustness and area efficiency, the waffle-type structure should be a promising layout for high-voltage ESD protection applications.