Abstract
This paper proposes a power-up calibration scheme to mitigate the offset of a capacitive-gain chopper instrumentation amplifier (CCIA), thus suppressing the offset-induced output ripple. In this design, the first stage of the error amplifier is formed by multiple identical slices. Before normal operation, the offset polarity of each slice is determined by reusing the second stage of the amplifier as a comparator. With such polarity information, slices of the first stage are regrouped to achieve a statistical offset reduction. The proposed amplifier has been fabricated in a standard <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.18~\mu \text{m}$ </tex-math></inline-formula> CMOS process with an area of 0.57 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , achieving an average peak-to-peak output ripple of 58 mV. The amplifier consumes <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.53~\mu \text{W}$ </tex-math></inline-formula> with a 1.2 V supply. Compared to the state-of-the-art, the calibration time of the proposed scheme is much shorter (14 clock cycles) and the overhead logic consumes no static power after calibration. In addition, the slicing technique provides an extra degree of freedom to the amplifier for bandwidth and noise scaling.
Highlights
D UE to manufacturing imperfections, intrinsic offset exists in all kinds of amplifiers
This paper presents an alternative technique to reduce the intrinsic offset during power-up with the help of amplifier slicing
Since the offset error of the second stage is suppressed by the gain of first stage, the intrinsic offset of the second stage can be omitted during the comparison
Summary
D UE to manufacturing imperfections, intrinsic offset exists in all kinds of amplifiers It results in a non-zero output when the amplifier input is zero. Popular practices to reduce offset include using large devices, performing dedicated layout matching, and conducting post-fabrication trimming [2] These techniques cannot withstand temperature variation and offset drift. Auto-zeroing suffers from noise folding because noise is stored together with the offset due to sampling Chopping is another offset reduction method that uses frequency translation [5]. This paper presents an alternative technique to reduce the intrinsic offset during power-up with the help of amplifier slicing.
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