Abstract
In this work we propose a test method to check the robustness of a Phase-Locked Loop (PLL). The goal is to identify weak devices that could fail under hostile operating conditions. We devise a “rigorous test flow” to measure the performance of a PLL device with “mimicked” hostile operating conditions. At the end of the test, the peak-to-peak jitter is used as a “robustness indicator” to guide the screening process of weak devices. Implementation of the proposed test flow on a PLL in a 90nm CMOS process demonstrates that obscure symptoms that might have escaped a simple traditional test can now be revealed.
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