Abstract
In this work we propose a test method to check the robustness of a Phase-Locked Loop (PLL). The goal is to identify weak devices that could fail under hostile operating conditions. We devise a “rigorous test flow” to measure the performance of a PLL device with “mimicked” hostile operating conditions. At the end of the test, the peak-to-peak jitter is used as a “robustness indicator” to guide the screening process of weak devices. Implementation of the proposed test flow on a PLL in a 90nm CMOS process demonstrates that obscure symptoms that might have escaped a simple traditional test can now be revealed.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.