Robust phase locked loops optimized for DSP implementation in power quality applications

Abstract

Phase locked loop (PLL) algorithms for grid synchronization are a very important part of the control in most of the grid-connected power converters applications. The performance of the PLL should not be much affected under distorted grid conditions: the presence of harmonics, unbalance, noise, etc in the inputs should not distort PLL measurements. This paper presents an optimized design approach of PLLs, both for single-phase and three-phase systems. The loop filter of the PLL sets its dynamic response; the loop filter should be tuned in order to achieve a correct tradeoff between transient response and harmonics/noise cancellation. This paper proposes the use of notch filters inside the loop in order to optimize the PLL performance; this approach is suitable both for single-phase and three-phase PLLs. Another novel interesting proposal of this paper is the implementation of the digitally controlled oscillator (DCO): the digital model of a sinusoidal oscillator is implemented, instead trigonometric functions. This reduces the needed digital resources without reducing the performance. This approach is specially useful for DSP-based control of power converters. The proposed PLLs have been implemented and tested in a fixed point DSP (TI TMS320LF2407) and also in a floating point microprocessor (PowerPC of the dSpace DS1103). The systems have been tested with different distorted inputs in order to check the validity of the design approaches and good results have been obtained.