RIBiT: Reduced Intra-flit Bit Transitions for Bufferless NoC

Abstract

In modern Tiled Chip Multicore Processor (TCMP) systems, Network on Chip (NoC) is the preferred interconnect solution to overcome scalability and performance bottleneck issues that conventional bus-based architectures face. For low to medium NoC traffic, the energy and area efficient bufferless router is a better design choice compared to buffered structures. Dynamic power contributes to the majority of total power dissipation during data transmission whereas only a fraction of it is due to leakage power. Self-switching and cross-coupling activities across NoC links are responsible for total dynamic power, of which latter is the prime contributor. In any NoC system, data encoding techniques are generally employed at Network Interface (NI) level to minimize power dissipation across NoC links. We propose a data encoding mechanism for bufferless NoCs to minimize bit transitions within the flit which will result in reduced dynamic link power. Our suggested approach leverages a modified version of Delta encoding technique where the flit is encoded into data differences by a configurable module placed inside NI of each core. No additional control lines and hence no changes to the network are required for our proposed encoding scheme. Experimental analysis done using Xilinx Vivado shows that our proposed design approach has significant reduction in intra-flit bit transitions in comparison to the baseline designs.