Abstract
In this paper, development of a wafer-level packaging (WLP) process suitable for RF–MEMS applications is presented. The packaging concept is based on a high-resistivity silicon capping substrate that is wafer-level bonded to an RF–MEMS device wafer providing MEMS device protection and vertical electrical signal interconnect. The capping substrate contains Cu-plated through-wafer electrical vias and optional through-substrate cavities allowing for hybrid integration. The RF–MEMS device wafer and the capping substrate are bonded using either solder reflow or an electrically conductive adhesive. After solder bump formation and singulation, this packaging solution results in surface-mount technology compatible components. Moreover, the presented WLP solution allows hybrid integration of additional IC dies that are flip-chip bonded within the capping substrate cavities.
Published Version
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